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Roma
OmniSwitch Troubleshooting Guide September 2005 page -23
• Separate paychecks for multicast
• Generates ingress coupons, receives egress coupons for backpressure capability
• Ingress coupon generation period: ~2 microseconds
• Paycheck generation period: 32.125 microseconds
• The BBUS provides access to individual Roma chips based on a chip index number
Functional Description
The Roma Driver’s primary responsibilities are to initialize, monitor, and support the central component
of the Eagle switch/router’s switching fabric system: a set of up to ten Roma ASICs, with exactly eight
operational during fabric operation.
The operational fabric consists of 8 slices for each connected Coronado ASIC (these 8 slices correspond
one-to-one with the 8 operational Roma ASICs). The fundamental logic for packet switching through the
fabric is contained in 5 basic architectural components:
• Link Control
• Calendar
• Multicast Vector Table
• IPC Mapping
• Flow Control
Link Control
This establishes that Roma-Coronado communication is working on each link and is aligned across the 8
fabric bit slices.
Calendar
Each fabric port has a calendar of unicast and multicast egress destinations for the corresponding Coro-
nado. There is a limited ability to designate dequeuing frequency for some destinations, affecting the
egress bandwidth allocated to destinations. During a given cycle of the Primary Cycle, a single calendar
entry for each fabric port is processed (in a specified order). During other cycles, other calendar entries are
processed. IPC packets are given absolute priority, so there are no calendar entries for IPC.
Multicast Vector Table
Indicates multicast domain membership for fabric ports. On fabric ingress, frames are put into a given
fabric port’s multicast FIFO based on this vector.
IPC Mapping
On ingress, Coronado IPC QIDs are identified based on agreed upon values (for Roma the values are
selected from offsets 12 through 15). On egress, an internal Roma table maps IPC QIDs to fabric ports
(one-to-one).