Filter
Top Products
C141-E090-01EN5 - 78
10) The device shall latch the host's CRC data from DD (15:0) on the negating edge of
DMACK-.
11) The device shall compare the CRC data received from the host with the results of its
own CRC calculation. If a miscompare error occurs during one or more Ultra DMA
bursts for any one command, at the end of the command the device shall report the
first error that occurred (see 5.5.5).
12) The device shall release DSTROBE within t
IORDYZ
after the host negates DMACK-.
13) The host shall not negate STOP no assert HDMARDY- until at least t
ACK
after
negating DMACK-.
14) The host shall not assert DIOR-, CS0-, CS1-, DA2, DA1, or DA0 until at least t
ACK
after negating DMACK.
b) Host terminating an Ultra DMA data in burst
The following steps shall occur in the order they are listed unless otherwise specifically
allowed (see 5.6.3.6 and 5.6.3.2 for specific timing requirements):
1) The host shall not initiate Ultra DMA burst termination until at least one data word of
an Ultra DMA burst has been transferred.
2) The host shall initiate Ultra DMA burst termination by negating HDMARDY-. The
host shall continue to negate HDMARDY- until the Ultra DMA burst is terminated.
3) The device shall stop generating DSTROBE edges within t
RFS
of the host negating
HDMARDY-.
4) If the host negates HDMARDY- within t
SR
after the device has generated a
DSTROBE edge, then the host shall be prepared to receive zero or one additional data
words. If the host negates HDMARDY- greater than t
SR
after the device has
generated a DSTROBE edge, then the host shall be prepared to receive zero, one or
two additional data words. The additional data words are a result of cable round trip
delay and t
RFS
timing for the device.
5) The host shall assert STOP no sooner than t
RP
after negating HDMARDY-. The host
shall not negate STOP again until after the Ultra DMA burst is terminated.
6) The device shall negate DMARQ within t
LI
after the host has asserted STOP. The
device shall not assert DMARQ again until after the Ultra DMA burst is terminated.
7) If DSTROBE is negated, the device shall assert DSTROBE within t
LI
after the host
has asserted STOP. No data shall be transferred during this assertion. The host shall
ignore this transition on DSTROBE. DSTROBE shall remain asserted until the Ultra
DMA burst is terminated.
8) The device shall release DD (15:0) no later than t
AZ
after negating DMARQ.
9) The host shall drive DD (15:0) no sooner than t
ZAH
after the device has negated
DMARQ. For this step, the host may first drive DD (15:0) with the result of its CRC
calculation (see 5.5.5).