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C141-E090-01EN5 - 20
(3) READ DMA (X'C8' or X'C9')
This command operates similarly to the READ SECTOR(S) command except for following
events.
• The data transfer starts at the timing of DMARQ signal assertion.
• The device controls the assertion or negation timing of the DMARQ signal.
• The device posts a status as the result of command execution only once at completion of
the data transfer.
When an error, such as an unrecoverable medium error, that the command execution cannot be
continued is detected, the data transfer is stopped without transferring data of sectors after the erred
sector. The device generates an interrupt using the INTRQ signal and posts a status to the host
system. The format of the error information is the same as the READ SECTOR(S) command.
In LBA mode
The logical block address is specified using the start head No., start cylinder No., and first
sector No. fields. At command completion, the logical block address of the last sector and
remaining number of sectors of which data was not transferred, like in the CHS mode, are set.
The host system can select the DMA transfer mode by using the SET FEATURES command.
1) Multiword DMA transfer mode 2:
Sets the FR register = X'03' and SC register = X'22' by the SET FEATURES command
2) Ultra DMA transfer mode 2:
Sets the FR register = X'03' and SC register = X'42' by the SET FEATURES command
At command issuance (I/O registers setting contents)
1F7
H
(CM) 1 1 0 0 1 0 0 R
1F6
H
(DH)
×
L
×
DV Start head No. /LBA [MSB]
1F5
H
(CH)
1F4
H
(CL)
1F3
H
(SN)
1F2
H
(SC)
1F1
H
(FR)
Start cylinder No. [MSB]/ LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx
R = 0 or 1