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Table 3-1: I/O Connector Signal Description (Part 1)........................ 21
Table 3-1: I/O Connector Signal Description (Part 2)........................ 22
Table 3-1: I/O Connector Signal Description (Part 3)........................ 23
Table 5-1: Gains and Analog Input Range ........................................ 33
Table 5-2: Analog Input Data Format ............................................... 39
Table 5-3: The corresponding Full Scale values for various Input
Voltage Ranges...............................................................39
Table 5-4: Analog Output Data Format ............................................ 43
Table 5-5: The corresponding Full Scale values for various Output
Voltage Ranges...............................................................43
Table D-1: PCI-1712/1712L register format (Part 1) .......................... 80
Table D-1: PCI-1712/1712L register format (Part 2) .......................... 81
Table D-1: PCI-1712/1712L register format (Part 3) .......................... 82
Table D-2: Register for channel number and A/D data ...................... 83
Table D-3: Register for A/D channel range setting ............................84
Table D-4: Gain Codes for the PCI-1712/1712L ................................ 85
Table D-5: Register for multiplexer control ........................................85
Table D-6: Register for A/D control/status ........................................87
Table D-7: Analog Input Acquisition Mode ........................................88
Table D-8: Register for clear interrupt and FIFO ...............................89
Table D-9: Register for interrupt and FIFO status ............................. 90
Table D-10: Register for D/A control ...................................................91
Table D-11: Analog output operation mode......................................... 92
Table D-12: Register for D/A channel 0/1 data ................................... 93
Table D-13: Register for 82C54 counter chip 0 ................................... 94
Table D-14: Register for 82C54 counter chip 1 ................................... 95
Table D-15: Register for counter gate and clock control/status........... 96
Table D-16 : Table of Cn1 to Cn0 register ............................................ 96
Table D-17: Table of Gn1 to Gn0 register............................................ 97
Table D-18: Table for CLK_SEL1 to CLK_SEL0 register .....................99