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Chapter 5
PCI-1712/1712L User’s Manual
Advantech Co., Ltd.
www.advantech.com
internal, and gate use for pulse
width measurement*/
outport(addr2_1712+0x22,0x80); //Set CNT1’s gate input as high
outport(addr2_1712+0x22,0x88); //Generate one clock to CNT1
outport(addr2_1712+0x22,0x71); /*Set CNT1’s clock source as
internal, gate use for pulse width
measurement, and negative
polarity*/
/*Reset pulse width measurement state machine, and check if CNT2’s
gate input receives the measured signal*/
while(1)
{
outport(addr2_1712+0x24,0x0031); //Generate a rising edge to
//reset the pulse
outport(addr2_1712+0x24,0x0131); //width measurement state
//machine
i = inport(addr2_1712+0x24) & 0x0800; /*Check if receiving
measured signal
from gate input of
CNT2*/
if (i == 0x0800) break ;
}
outport(addr2_1712+0x22,0x0071); //Generate a rising edge to reset
//the pulse
outport(addr2_1712+0x22,0x0171); //width measurement state
//machine
//CNT2’s gate input receiving the measured signal, check if finished
while(1)
{
i = inport(addr2_1712+0x24) & 0x0800;
if(i == 0x0000) break; //CNT2’s gate input is low
}