Filter
Top Products
– 96 –
APPENDIX D
PCI-1712/1712L User’s Manual
Advantech Co., Ltd.
www.advantech.com
D.14 Counter gate and clock control/status — Write/
Read BASE+20 to 26
Table D-15: Register for counter gate and clock control/status
Cn1 to Cn0 Counter clock source control register n = 0,1,2
Table D-16 : Table of Cn1 to Cn0 register
[Cn1: Cn0] = [0, 0], write CQn to set the counter clock. Refer
to CQn description.
[Cn1: Cn0] = [0, 1], The internal clock is generated by an on-
board oscillator.
[Cn1: Cn0] = [1, 0], External clock is on connector
CNTn_CLK (n = 0, 1, 2).
[Cn1: Cn0] = [1, 1], The clock source of every counter
1nC 0nC gninaeM
0 0 nQCybtessikcolC
0 1 kcolclanretnimorfsemockcolC
1 0 kcolclanretxemorfsemockcolC
1 1 tuos’retnuocsuoiverpmorfsemockcolC
.ddAesaB 51 41 31 21 11 01 9 8 7 6 5 4 3 2 1 0
02
W
lortnockcolcdnaetag0retnuoC
0RG 0QG 0PG 10G 00G 0QC 0PC 10C 00C
R
sutatskcolcdnaetag0retnuoC
-TAG
0SE
0KLC 0TUO
-TAG
0E
0QG 0PG 10G 00G 0QC 0PC 10C 00C
22
W
lortnockcolcdnaetag1retnuoC
1RG 1QG 1PG 11G 01G 1QC 1PC 11C 01C
R
sutatskcolcdnaetag1retnuoC
-TAG
1SE
1KLC 1TUO
-TAG
1E
1QG 1PG 11G 01G 1QC 1PC 11C 01C
42
W
lortnockcolcdnaetag2retnuoC
2RG 2QG 2PG 12G 02G 2QC 2PC 12C 02C
R
sutatskcolcdnaetag2retnuoC
-TAG
2SE
2KLC 2TUO
-TAG
2E
2QG 2PG 12G 02G 2QC 2PC 12C 02C
62
W
retsigertcelesecruoskcolclanretniretnuoC
-_KLC
1LES
-_KLC
0LES
R
A/N