Filter
Top Products
– 100 –
APPENDIX D
PCI-1712/1712L User’s Manual
Advantech Co., Ltd.
www.advantech.com
.ddAesaB 51 41 31 21 11 01 9 8 7 6 5 4 3 2 1 0
C2 W
ataddnadnammocnoitarbilaC
3MC 2MC 1MC 0MC 7D 6D 5D 4D 3D 2D 1D 0D
DI15 to DI0 Digital input data register
DI0 is the least significant bit (LSB) of the digital input data.
DI15 is the most significant bit (MSB) of the digital input
data.
D.16 Digital I/O configuration registers — Write/Read
BASE+2A
Table D-20: Register for digital I/O configuration
DIO_C1 to DIO_C0 Digital I/O configuration register
Table D-21: Register for digital I/O configuration
When all digital I/O channels are set as output channels, users can
confirm the data output status by reading back from digital input data
registers.
D.17 Calibration command registers — Write BASE+2C
Table D-22: Register for calibration command
.ddAesaB 51 41 31 21 11 01 9 8 7 6 5 4 3 2 1 0
A2
W
retsigernoitarugifnocO/IlatigiD
_OID
1C
_OID
0C
R
retsigernoitarugifnocO/IlatigiD
_OID
1C
_OID
0C
1C_OID 0C_OID
gninaeM
)8ot51tib(etyBhgiH )0ot7tib(etyBwoL
0 0 tuptuO tuptuO
0 1 tuptuO tupnI
1 0 tupnI tuptuO
1 1 tupnI tupnI