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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (
µ
PD78054Y Subseries)
R/W ACKE Acknowledge Signal Automatic Output Control
Note 1
0 Disabled (with ACKT enabled). Used when receiving data in the 8-clock wait mode or when transmitting
data.
Note 2
1 Enabled.
After completion of transfer, acknowledge signal is output in synchronization with the 9th falling edge of
SCL clock (automatically output when ACKE = 1). However, not automatically cleared to 0 after
acknowledge signal output. Used for reception when the 9-clock wait mode is selected.
R ACKD Acknowledge Detection
0 Clear Conditions
• When transfer start instruction is executed
• When CSIE0 = 0
• When RESET input is applied
1 Set Conditions
• When acknowledge signal is detected at the rising edge of SCL clock after completion of transfer
R/W BSYE Control of N-ch Open-Drain Output for Transmission in I
2
C Bus Mode
Note 4
Note 3
0 Output enabled (transmission)
1 Output disabled (reception)
Notes 1. This setting must be performed prior to transfer start.
2. In the 8-clock wait mode, use ACKT for output of the acknowledge signal after normal data reception.
3. The busy mode can be released by the start of a serial interface transfer or reception of an address
signal. However, the BSYE flag is not cleared.
4. When using the wake-up function, be sure to set BSYE to 1.
Remark CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)