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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS
21.4.3 Software interrupt request acknowledge operation
A software interrupt request is acknowledged by BRK instruction execution. Software interrupt cannot be disabled.
If a software interrupt request is acknowledged, the contents is saved in the stacks, program status word (PSW)
and program counter (PC), in that order, the IE flag is reset to 0 and the contents of the vector tables (003EH and
003FH) are loaded into PC and branched.
Return from the software interrupt is possible with the RETB instruction.
Caution Do not use the RETI instruction for returning from the software interrupt.
21.4.4 Multiple interrupt servicing
Acknowledging another interrupt request while servicing an interrupt is called a multiple interrupt.
A multiple interrupt is not generated unless interrupt request acknowledge enabled state (IE = 1) is set (except
non-maskable interrupt). When an interrupt request is acknowledged, interrupt request becomes acknowledge
disabled state (IE = 0). Therefore, to enable a multiple interrupt, set IE flag to (1) with EI instruction during interrupt
servicing, and set interrupt enable state.
In some cases, a multiple interrupt is not enabled even during interrupt enable state. It is controlled with the interrupt
priority. There are two interrupt priorities : default priority and programmable priority. The multiple interrupt is
controlled with programmable priority.
If an interrupt request of the same priority as or a higher priority than the interrupt currently being serviced is
generated, it is acknowledged as a multiple interrupt. If an interrupt request of the priority lower than the interrupt
currently being serviced is generated, it is not acknowledged as a multiple interrupt.
An interrupt request that is not acknowledged due to interrupt disable or low priority is reserved. The reserved
interrupt request is acknowledged after the current interrupt servicing is completed and one instruction of the main
processing is executed.
A multiple interrupt is not acknowledged while a non-maskable interrupt is being serviced.
Table 21-4 shows the interrupt requests that are capable of multiple interrupts, and Figure 21-16 shows examples
of multiple interrupts.
Table 21-4. Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing
Maskable Interrupt Request
PR = 0 PR = 1
IE = 1 IE = 0 IE = 1 IE = 0
Non-maskable interrupt D D D D D
ISP = 0 E E D D D
ISP = 1 E E D E D
Software interrupt E E D E D
Remarks 1. E : Multiple interrupt enable
2. D : Multiple interrupt disable
3. ISP and IE are the flags contained in PSW
ISP=0 : An interrupt with higher priority is being serviced
ISP=1 : An interrupt request is not accepted or an interrupt with lower priority is being
serviced
IE=0 : Interrupt request acknowledge is disabled
IE=1 : Interrupt request acknowledge is enabled
4. PR is a flag contained in PR0L, PR0H, and PR1L
PR=0 : Higher priority level
PR=1 : Lower priority level
Interrupt being
Serviced
Non-maskable
Interrupt
Request
Multiple Interrupt
Request
Maskable interrupt