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CHAPTER 25 ROM CORRECTION
25.7 Cautions on ROM Correction
(1) Address values set in correction address registers 0 and 1 (CORAD0, CORAD1) must be addresses where
instruction codes are stored.
(2) Correction address registers 0 and 1 (CORAD0, CORAD1) should be set when the correction enable flag
(COREN0, COREN1) is 0 (when the correction branch is in disabled state). If address is set to CORAD0 or
CORAD1 when COREN0 or COREN1 is 1 (when the correction branch is in enabled state), the correction
branch may start with the different address from the set address value.
(3) Do not set the address value of instruction immediately after the instruction that sets the correction enable
flag (COREN0, COREN1) to 1, to correction address register 0 or 1 (CORAD0, CORAD1) ; the correction
branch may not start.
(4) Do not set the address value in table area of table reference instruction (CALLT instruction) (0040H to 007FH),
and the address value in vector table area (0000H to 003FH) to correction address registers 0 and 1 (CORAD0,
CORAD1).
(5) Do not set two addresses immediately after the instructions shown below to correction address registers 0
and 1 (CORAD0, CORAD1). (that is, when the mapped terminal address of these instructions is N, do not
set the address values of N+1 and N+2.)
• RET
• RETI
• RETB
• BR $addr16
• STOP
• HALT