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CHAPTER 18 SERIAL INTERFACE CHANNEL 1
(c) Automatic data transmit/receive interval specify register (ADTI)
This register sets the automatic data transmit/receive function data transfer interval.
ADTI is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTI to 00H.
Notes 1. The interval is dependent only on CPU processing.
2. The data transfer interval includes an error. The data transfer minimum and maximum intervals
are found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if a
minimum which is calculated by the following expressions is smaller than 2/f
SCK, the minimum
interval time is 2/f
SCK.
Minimum = (n+1) × + + , Maximum = (n+1) × ++
Cautions 1. Do not write data to ADTI during operation of automatic data transmit/receive
function.
2. Zero must be set in bits 5 and 6.
3. To control the data transfer interval by means of automatic transmission/reception
with ADTI, busy control (refer to 18.4.3 (4) (a) Busy control option) is disabled.
Remarks 1. f
XX : Main system clock frequency (fX or fX/2)
2. f
X : Main system clock oscillation frequency
3. fSCK : Serial clock frequency
fXX
fXX
2
6
fXX
fSCK
28
0.5
26
f
XX
36
1.5
fSCK
Data Transfer Interval Specification (fXX = 5.0 MHz Operation)
ADTI4 ADTI3 ADTI2 ADTI1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Minimum
Note 2
18.4
s + 0.5/fSCK
31.2
s + 0.5/fSCK
44.0
s + 0.5/fSCK
56.8
s + 0.5/fSCK
69.6
s + 0.5/fSCK
82.4
s + 0.5/fSCK
95.2
s + 0.5/fSCK
108.0
s + 0.5/fSCK
120.8
s + 0.5/fSCK
133.6
s + 0.5/fSCK
146.4
s + 0.5/fSCK
159.2
s + 0.5/fSCK
172.0
s + 0.5/fSCK
184.8
s + 0.5/fSCK
197.6
s + 0.5/fSCK
210.4
s + 0.5/fSCK
Maximum
Note 2
20.0
s + 1.5/fSCK
32.8
s + 1.5/fSCK
45.6
s + 1.5/fSCK
58.4
s + 1.5/fSCK
71.2
s + 1.5/fSCK
84.0
s + 1.5/fSCK
96.8
s + 1.5/fSCK
109.6
s + 1.5/fSCK
122.4
s + 1.5/fSCK
135.2
s + 1.5/fSCK
148.0
s + 1.5/fSCK
160.8
s + 1.5/fSCK
173.6
s + 1.5/fSCK
186.4
s + 1.5/fSCK
199.2
s + 1.5/fSCK
212.0
s + 1.5/fSCK
65432107
Symbol
ADTI ADTI7 0 0 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0
FF6BH 00H R/W
Address After Reset R/W
ADTI7
0
Data Transfer Interval Control
No control of interval by ADTI
Note 1
Control of interval by ADTI (ADTI0 to ADTI4)
1
ADTI0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ