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CHAPTER 19 SERIAL INTERFACE CHANNEL 2
(3) UART mode cautions
(a) When bit 7 (TXE) of the asynchronous serial interface mode register (ASIM) is cleared and the
transmission operation is stopped during transmission, be sure to set the transmit shift register (TXS) to
FFH, then set the TXE to 1 before executing the next transmission.
(b) When bit 6 (RXE) of ASIM is cleared and the receive operation is stopped during reception, the state of
the receive buffer register (RXB) and whether the receive completion interrupt request (INTSR) is
generated depend on the timing of clearing. Figure 19-11 shows the timing.
Figure 19-11. The State of Receive Buffer Register (RXB) and Whether
the Receive Completion Interrupt Request (INTSR) is Generated
When RXE is set to 0 at a time indicated by <1>, RXB holds the previous data and does not generate INTSR.
When RXE is set to 0 at a time indicated by <2>, RXB renews the data and does not generate INTSR.
When RXE is set to 0 at a time indicated by <3>, RXB renews the data and generates INTSR.
ParityRxD Pin
RXB
INTSR
<3><1>
<2>