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2 Troubleshooting Procedures 2.4 System Board Troubleshooting
2-24 [CONFIDENTIAL] PORTEGE A600 Maintenance Manual (960-710)
Table 2-5 Debug port error status (2/8)
System BIOS IRT processing
Debug
Code
BIOS processing
Target Device IC No.
CPU setup
Initialization of ICH, MCH, and Super
I/O
setup of SD controller
F100
setup of PIT
CPU
ICH(PCIRegister,PITContro
ller)
MCH(PCIRegister)
SDController
BIOSROM
IC1050(CPU)
IC1600(ICH)
IC1200(MCH)
IC2000(SDController)
IC3001(BIOS ROM)
F101
Memory initialization
Memory error
setup for using RAM area
check memory error of RAM area
F102
memory error
MCH(PCIRegister)
RAM(SPD,Memory)
ICH(PCIRegister,CMOS)
CPU
BIOSROM
IC1200(MCH)
IC1420,1421,1430,1431(RAM
)
IC1440,1441,1450,1451(RAM
)
CN1410(RAM Conn.)
IC1600(ICH)
IC1050(CPU)
IC3001(BIOS ROM)
CPU setup
CMOS setup
F103
CMOS error
CPU
ICH(CMOS)
BIOSROM
IC1050(CPU)
IC1600(ICH)
IC3001(BIOS ROM)
Resume branch
BIOS processing reading
F104
ROM read error
ICH(CMOS)
BIOSROM
RAM
IC1200(MCH)
IC3001(BIOS ROM)
IC1420,1421,1430,1431(RAM
)
IC1440,1441,1450,1451(RAM
)
CN1410(RAM Conn.)
F105 check of BIOS processing
EC/KBC(EC)
TPM
CPU
IC3200(EC/KBC)
IC3300(TPM)
IC1050(CPU)
RAM setup
F106
Initialization of ICH (APIC)
CPU
ICH(CMOS,PICController,I
/O,MEM I/O)
RAM
IC1050(CPU)
IC1600(ICH)
IC1420,1421,1430,1431(RAM
)
IC1440,1441,1450,1451(RAM
)
CN1410(RAM Conn.)
Initialization of ICH (PIT)
PIT initialization error
CPU check
check of ROM data
SMI setup
Part number data distinction
Panel distinction
CMOS check
Clock generator setup
F107
CPU initialization
CPU
ICH(PITController,MEM
I/O,CMOS,I/O)
Clock Generator
IC1050(CPU)
IC1600(ICH)
IC1000(Clock Generator)