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Glossary
Glossary–2
VX1410A & VX1420A IntelliFrame Mainframe Instruction Manual
Butch Plate
A connector plate that optionally connects to the rear of the cable tray
options. The plate can be modified to accept cable connectors thus reducing
the number of cables under the IntelliFrame Mainframe.
Client
In shared memory protocol (SMP), that half of an SMP channel that does not
control the shared memory buffers.
CLK10
A 10 MHz, ±100 ppm, individually buffered (to each module slot),
differential ECL system clock that is sourced from Slot 0 and distributed to
Slots 1–12 on P2. It is distributed to each module slot as a single source,
single destination signal with a matched delay of under 8 ns.
CLK100
A 100 MHz, ±100 ppm, individually buffered (to each module slot),
differential ECL system clock that is sourced from Slot 0 and distributed to
Slots 1–12 on P3. It is distributed to each module slot in synchronous with
CLK10 as a single source, single destination signal with a maximum system
timing skew of 2 ns, and a maximum total delay of 8 ns.
Commander
In the VXIbus interface, a device that controls another device (a servant). A
commander may be a servant of another commander.
Command
A directive to a device. There are three types of commands:
In Word Serial Protocol, a 16-bit imperative to a servant from its com-
mander.
In Shared Memory Protocol, a 16-bit imperative from a client to a server, or
vice versa.
In a Message, an ASCII-coded, multi-byte directive to any receiving device.
Communication Registers
In word serial protocol, a set of device registers that are accessible to the
commander of the device. Such registers are used for inter-device commu-
nications, and are required on all VXIbus message-based devices.
Configuration Registers
A set of registers that allow the system to identify a (module) device type,
model, manufacturer, address space, and memory requirements. In order to
support automatic system and memory configuration, the VXIbus standard
specifies that all VXIbus devices have a set of such registers, all accessible
from P1 on the VMEbus.