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21264/EV68A Hardware Reference Manual
Cache and External Interfaces 4–51
Bcache Port
4.8.4.1 BcAdd_H[23:4]
The BcAdd_H[23:4] pins are high drive outputs that provides the index for the Bcache.
The 21264/EV68A supports Bcache sizes of 1MB, 2MB, 4MB, 8MB, and 16MB.
Table 4–42 lists the values to be programmed into Cbox CSRs BC_ENABLE[0] and
BC_SIZE[3:0] to support each size of the Bcache.
When the Cbox CSR BC_BANK_ENABLE[0] is not set, the unused BcAdd_H[23:4]
pins are tied to zero. For example, when configured as a 4MB cache, the 21264/EV68A
never changes BcAdd_H[23:22] from logic zero, and when BC_BANK_ENABLE[0]
is asserted, the 21264/EV68A drives the complement of the MSB index on the next
higher BcAdd_H pin.
4.8.4.2 Bcache Control Pins
The Bcache control pins (BcLoad_L, BcDataWr_L, BcDataOE_L, BcTagWr_L,
BcTagOE_L) are controlled using Cbox CSRs BC_BURST_MODE_ENABLE[0] and
BC_PENTIUM_MODE[0].
Table 4–43 shows the four combinations of Bcache control pin behavior obtained using
the two CSRs.
Table 4–44 lists the combination of control pin assertion for
RAM_TYPE A.
Table 4–42 Programming the Bcache to Support Each Size of the Bcache
BC_ENABLE[0] BC_SIZE[3:0] Bcache Size
1 0000 1MB
1 0001 2MB
100114MB
1 0111 8MB
1 1111 16MB
Table 4–43 Programming the Bcache Control Pins
BC_PENTIUM_MODE BC_BURST_MODE_ENABLE RAM_TYPE
00 RAM_TYPEA
01 RAM_TYPEB
1 0 Unsupported
1 1 Unsupported
Table 4–44 Control Pin Assertion for RAM_TYPE A
TYPE_A NOP RA0 RA1 RA2 RA3 NOP NOP WA0 WA1 WA2 WA3 NOP
BcLoad_L HHHHHHHHHHHH
BcDataOE_L HLLLLHHLLLLH
BcDataWr_L HHHHHHHLLLLH
BcTagOE_L HLHHHHHLHHHH
BcTagWr_L HHHHHHHLHHHH