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21264/EV68A Hardware Reference Manual
ix
11.5.2 SROMInitialization..................................................... 11–5
11.5.2.1 SerialInstructionCacheLoadOperation ................................ 11–6
11.6 Notes on IEEE 1149.1 Operation and Compliance ............................... 11–7
A Alpha Instruction Set
A.1 AlphaInstructionSummary.................................................. A–1
A.2 Reserved Opcodes . ....................................................... A–8
A.2.1 Opcodes Reserved for Compaq........................................... A–8
A.2.2 Opcodes Reserved for PALcode .......................................... A–9
A.3 IEEEFloating-PointInstructions.............................................. A–9
A.4 VAXFloating-PointInstructions............................................... A–11
A.5 Independent Floating-Point Instructions . . ...................................... A–11
A.6 OpcodeSummary......................................................... A–12
A.7 RequiredPALcodeFunctionCodes........................................... A–13
A.8 IEEEFloating-PointConformance ............................................ A–14
B 21264/EV68A Boundary-Scan Register
B.1 Boundary-Scan Register . . .................................................. B–1
B.1.1 BSDL Description of the Alpha 21264/EV68A Boundary-Scan Register . . .......... B–1
C Serial Icache Load Predecode Values
D PALcode Restrictions and Guidelines
D.1 Restriction 1 : Reset Sequence Required by Retire Logic and Mapper............... D–1
D.2 Restriction 2 : No Multiple Writers to IPRs in Same Scoreboard Group ............... D–8
D.3 Restriction 4 : No Writers and Readers to IPRs in Same Scoreboard Group .......... D–8
D.4 Guideline 6 : Avoid Consecutive Read-Modify-Write-Read-Modify-Write . . .......... D–9
D.5 Restriction 7 :ReplayTrap,InterruptCodeSequence,andSTF/ITOF............... D–9
D.6 Restriction 9 : PALmode Istream Address Ranges . . . ........................... D–10
D.7 Restriction 10:DuplicateIPRModeBits ....................................... D–10
D.8 Restriction 11: Ibox IPR Update Synchronization ................................ D–11
D.9 Restriction 12: MFPR of Implicitly-Written IPRs EXC_ADDR, IVA_FORM, and EXC_SUM D–11
D.10 Restriction13:DTBFillFlowCollision......................................... D–11
D.11 Restriction14:HW_RET ................................................... D–11
D.12 Guideline16:JSR-BADVA................................................. D–12
D.13 Restriction17:MTPRtoDTB_TAG0/DTB_PTE0/DTB_TAG1/DTB_PTE1 ............. D–12
D.14 Restriction 18: No FP Operates, FP Conditional Branches, FTOI, or STF in Same Fetch Block as
HW_MTPR .............................................................. D–12
D.15 Restriction 19: HW_RET/STALL After Updating the FPCR by way of MT_FPCR in PALmode D–12
D.16 Guideline 20 : I_CTL[SBE] Stream Buffer Enable................................ D–12
D.17 Restriction21:HW_RET/STALLAfterHW_MTPRASN0/ASN1...................... D–12
D.18 Restriction22:HW_RET/STALLAfterHW_MTPRIS0/IS1.......................... D–13
D.19 Restriction23:HW_ST/P/CONDITIONALDoesNotCleartheLockFlag............... D–13
D.20 Restriction 24: HW_RET/STALL After HW_MTPR IC_FLUSH, IC_FLUSH_ASM, CLEAR_MAP
....................................................................... D–14
D.21 Restriction25:HW_MTPRITB_IAAfterReset................................... D–14
D.22 Guideline 26: Conditional Branches in PALcode ................................. D–14
D.23 Restriction27:Resetof‘Force-FailLockFlag’StateinPALcode..................... D–15
D.24 Restriction 28: Enforce Ordering Between IPRs Implicitly Written by Loads and Subsequent Loads
....................................................................... D–15
D.25 Guideline29:JSR,JMP,RET,andJSR_CORinPALcode......................... D–15