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21264/EV68A Hardware Reference Manual
clock offset (or clkoffset)
The delay intentionally added to the forwarded clock to meet the setup and hold
requirements at the Receive Flop.
CMOS
Complementary metal-oxide semiconductor. A silicon device formed by a process that
combines PMOS and NMOS semiconductor material.
conditional branch instructions
Instructions that test a register for positive/negative or for zero/nonzero. They can also
test integer registers for even/odd.
control and status register (CSR)
A device or controller register that resides in the processor’s I/O space. The CSR ini-
tiates device activity and records its status.
CPI
Cycles per instruction.
CPU
See central processing unit.
CSR
See control and status register.
cycle
One clock interval.
data bus
A group of wires that carry data.
Dcache
Data cache. A cache reserved for storage of data. The Dcache does not contain instruc-
tions.
DDR
Dual-data rate. A dual-data rate SSRAM can provide data on both the rising and falling
edges of the clock signal.
denormal
An IEEE floating-point bit pattern that represents a number whose magnitude lies
between zero and the smallest finite number.
DIP
Dual inline package.