Compaq EV68A Network Card User Manual


 
2–38 Internal Architecture
21264/EV68A Hardware Reference Manual
Design Examples
2.15.1 AMASK
The 21264/EV68A returns the AMASK instruction values provided in Table 2–15. The
I_CTL register reports the 21264/EV68A pass level (see I_CTL[CHIP_ID], Section
5.2.15).
The AMASK bit definitions provided in Table 2–15 are defined in Table 2–16.
2.15.2 IMPLVER
For the 21264/EV68A, the IMPLVER instruction returns the value 2.
2.16 Design Examples
The 21264/EV68A can be designed into many different uniprocessor and multiproces-
sor system configurations. Figures 2–12 and 2–13 illustrate two possible configura-
tions. These configurations employ additional system/memory controller chipsets.
Figure 2–12 shows a typical uniprocessor system with a second-level cache. This sys-
tem configuration could be used in standalone or networked workstations.
Table 2–15 21264/EV68A AMASK Values
21264/EV68A Pass Level AMASK Feature Mask Value
See I_CTL[CHIP_ID], Table 5–11 1307
16
Table 2–16 AMASK Bit Assignments
Bit Meaning
0 Support for the byte/word extension (BWX)
The instructions that comprise the BWX extension are LDBU, LDWU, SEXTB,
SEXTW, STB, and STW.
1 Support for the square-root and floating-point convert extension (FIX)
The instructions that comprise the FIX extension are FTOIS, FTOIT, ITOFF, ITOFS,
ITOFT, SQRTF, SQRTG, SQRTS, and SQRTT.
2 Support for the count extension (CIX)
The instructions that comprise the CIX extension are CTLZ, CTPOP, and CTTZ.
8 Support for the multimedia extension (MVI)
The instructions that comprise the MVI extension are MAXSB8, MAXSW4,
MAXUB8, MAXUW4, MINSB8, MINSW4, MINUB8, MINUW4, PERR, PKLB,
PKWB, UNPKBL, and UNPKBW.
9 Support for precise arithmetic trap reporting in hardware. The trap PC is the same as
the instruction PC after the trapping instruction is executed.
12 Support for using a prefetch with modify intent to improve the performance of the
first attempt to acquire a lock. When clear, indicates possible prefetch error with
locks, described in waiver 10 to the Alpha Architecture and in the prefetch section of
the appropriate processor (21264/EV6 and 21264/EV67) documents.