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7–18 Initialization and Configuration
21264/EV68A Hardware Reference Manual
Reset State Machine
RAMP2 Triggered by the duration counter reaching 4108 cycles, the X
div
and Z
div
divisors are
changed to 1 and 2, respectively, and the frequency is increased. The duration counter is
reloaded to count 8205-cycles.
WAIT_ClkFwdRst0 Triggered by the duration counter reaching 8205 cycles (or by the deassertion of
Reset_L while in the WAIT_RESET state). 21264/EV68A asserts SromOE_L and
waits for SYSTEM to deassert ClkFwdReset_H. The deassertion must be synchronous
to a falling edge of FrameClk_H. 21264/EV68A uses this deassertion to begin BiST
and SROM load at a predictable time. 21264/EV68A samples and generates an internal,
aligned copy of FrameClk_H, and, in turn, uses this clock to sample ClkFwdReset_H.
WAIT_BiST BiST and SROM load is started. The SROM first loads the Write-once chain and then
reads the number of bits of Icache data to load.
WAIT_BiSI This state is entered when 'waking up' from sleep mode. 21264/EV68A receives an
external interrupt, ramps the PLL, synchronously samples a transition on
ClkFwdReset_H, and runs built-in self-initialization to clear the internal caches. Built-
in self-test is not performed and the SROM is not loaded.
WAIT_ClkFwdRst1 Entered when the appropriate amount of BiST and SROM loading has been completed.
21264/EV68A deasserts SromOE_L and waits for SYSTEM to deassert
ClkFwdReset_H. The deassertion must be synchronous to a rising edge of
FrameClk_H. 21264/EV68A uses this synchronous event to reset the clock forwarding
interface and deassert internal reset. 21264/EV68A subsequently begins running code
(either preloaded in the SROM or located in memory) and begins system transactions.
RUN Chip is running software, interface is reset, and system transactions can be processed.
From power-up, the Icache sets are enabled and contain bootstrap code loaded from the
SROM; 21264/EV68A executes code from Icache. From wake-up, the Icache sets are
disabled and 21264/EV68A fetches and executes code from DRAM.
WAIT_RESET Triggered by duration counter reaching 264 cycles, or when Reset_L is asserted when in
WAIT_INTERRUPT state. 21264/EV68A waits in this state until Reset_L is deasserted,
at which point, the PLL starts to ramp up again.
FAULT_RESET ClkFwdReset is asserted while the 21264/EV68A is running. The 21264/EV68A inter-
nally resets a minimum amount of internal state, waits for clock forward reset deasser-
tion, and begins fetching code at PAL_BASE + 0x780.
DOWN1 21264/EV68A was in a state in which GCLK was at its highest speed and Reset_L was
asserted. Internal chip functions are reset and the internal duration counter is set to 8205
cycles. The purpose of this sequence is to down-ramp the clocks in anticipation of power
being removed. If power is not removed (that is, reset is being toggled), 21264/EV68A
ramps the clocks back to the original speed.
This state is also entered when software writes the I_CTL internal processor register to
sleep mode.
Table 7–11 21264/EV68A Reset State Machine State Descriptions (Continued)
State Name Description