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8–8 Error Detection and Error Handling
21264/EV68A Hardware Reference Manual
Memory/System Port Single-Bit Data Correctable ECC Error
•
A machine check (MCHK) is posted and taken immediately. The PALcode machine
check handler performs a scrubbing operation as described in Section D.36 to
ensure that the origination point of the error is corrected.
Note: Also, a corrected read data (CRD) error is posted, when enabled, in case
this error is in a speculative path and the MCHK is removed. The CRD
error PALcode reads the status to detect this condition and scrubs the block.
In the normal MCHK flow, the PALcode clears the pending CRD error.
8.10.2 Dcache Fill from Memory
If the quadword in error is not used to satisfy a load instruction, no hardware
recovery flow is invoked. The quadword in error, and its associated check bits, are writ-
ten into the Dcache. However, status is logged as shown in the bulleted list below and a
corrected read data (CRD) error interrupt is posted, when enabled. PALcode may
choose to correct the error by scrubbing the block. If the error is not corrected by PAL-
code at the time, the error will be detected and corrected by a load/victim operation.
If the quadword in error is used to satisfy a load instruction, then the flow is very simi-
lar to that used for a Dcache ECC error:
• The load instruction’s destination register is written with incorrect data; however,
the load queue will retain the state associated with the load instruction.
• A consumer of the load instruction’s data may be issued before the error is
recognized; however, the Ibox will invoke a replay trap at an instruction that is
older than (or equal to) any instruction that consumes the load instruction’s data.
The Ibox stalls the replayed Istream in the map stage of the pipeline until the error
is corrected.
• With a READ_ERR read type from the Mbox for the load instruction in error, the
Cbox scrubs the block in the Dcache by evicting the block into the victim buffer
and writing it back into the Dcache.
• C_STAT[DSTREAM_MEM_ERR] is set.
• C_ADDR contains bits [42:6] of the system memory fill address of the block that
contains the error.
• C_SYNDROME_0[7:0] and C_SYNDROME_1[7:0] contain the syndrome of
quadword 0 and 1, respectively, of the octaword subblock that contains the error.
• The load queue retries the load instruction and rewrites the register.
• DC_STAT[ECC_ERR_LD] is set.
• A corrected read data (CRD) error interrupt is posted, when enabled.
Note: Errors in speculative load instructions cause a CRD error to be posted but
the data is not scrubbed by hardware. The PALcode cannot scrub the data
because C_STAT is zero, and C_ADDR does not have the address of the
block with the error.