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21264/EV68A Hardware Reference Manual
Internal Processor Registers 5–33
Cbox CSRs and IPRs
5.4.1 Cbox Data Register – C_DATA
Figure 5–35 shows the Cbox data register.
Figure 5–35 Cbox Data Register
Table 5–22 describes the Cbox data register fields.
5.4.2 Cbox Shift Register – C_SHFT
Figure 5–36 shows the Cbox shift register.
Figure 5–36 Cbox Shift Register
Table 5–23 describes the Cbox shift register fields.
5.4.3 Cbox WRITE_ONCE Chain Description
The WRITE_ONCE chain order is contained in Table 5–24. In the table:
• Many CSRs are duplicated for ease of hardware implementation. These CSRs are
indicated in italics. They must be written with values that are identical to the values
written to the original CSRs.
Table 5–22 Cbox Data Register Fields Description
Name Extent Type Description
Reserved [63:6] — —
C_DATA[5:0] [5:0] RW Cbox data register. A HW_MTPR instruction to this register causes six
bits of data to be placed into a serial shift register. When the
HW_MTPR instruction is retired, the data is shifted into the Cbox. After
the Cbox shift register has been accessed, performing a HW_MFPR
instruction to this register will return six bits of data.
Table 5–23 Cbox Shift Register Fields Description
Name Extent Type Description
Reserved [63:1] — —
C_SHIFT [0] W1 Writing a 1 to this register bit causes six bits of Cbox IPR data to shift into
the Cbox data register. Software can then use a HW_MFPR read operation
to the Cbox data register to read the six bits of data.
63 65 0
C_DATA[5:0]
LK
99
-
00
4
3
A
63 10
C_SHIFT
LK
99
-
00
44A