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9–8 Electrical Data
21264/EV68A Hardware Reference Manual
AC Characteristics
BcDataInClk_H[7:0] I_DA NA NA NA NA 45-55%
BcDataOutClk_H[3:0] O_PP EV6Clk_x NA NA ± 350 ps
BcDataOutClk_L[3:0] O_PP EV6Clk_x NA NA ± 350 ps
BcTag_H[42:20] B_DA_PP BcTagInClk_H 400 ps 400 ps NA NA 1.0 V/ns
BcTagDirty_H B_DA_PP BcTagInClk_H 400 ps 400 ps NA NA 1.0 V/ns
BcTagOutClk_x 38-63%
8
NA
BcTagParity_H B_DA_PP BcTagInClk_H 400 ps 400 ps NA NA 1.0 V/ns
BcTagShared_H B_DA_PP BcTagInClk_H 400 ps 400 ps NA NA 1.0 V/ns
BcTagOutClk_x 40-60%
9
NA
BcTagValid_H B_DA_PP BcTagInClk_H 400 ps 400 ps NA NA 1.0 V/ns
BcTagOutClk_x NA NA ± 300 ps
6
45-55% NA
BcTagOE_L O_PP
BcTagWr_L O_PP
BcTagInClk_H I_DA NA NA NA NA 45-55%
BcTagOutClk_x O_PP EV6Clk_x NA NA ± 350 ps
IRQ_H[5:0] I_DA DCOK_H 10 ns
11
10 ns
11
NA NA 100 mV/ns
Reset_L
12
I_DA NA NA NA NA 100 mV/ns
DCOK_H
13
I_DA NA NA NA NA 100 mV/ns
PllBypass_H
14
I_DA NA NA NA NA 100 mV/ns
ClkIn_x
15
I_DA_CLK NA NA NA 40–60%
16
1.0 V/ns
FrameClk_x
17
I_DA_CLK ClkIn_x 400 ps 400 ps NA NA 1.0 V/ns
EV6Clk_x
18
O_PP_CLK ClkIn_x NA NA ±1.0 ns YDiv±5% NA
EV6Clk_x
19
Cycle Compression Specification: See Note 19
ClkFwdRst_H I_DA FrameClk_x 400 ps 400 ps NA NA 1.0 V/ns
SromData_H I_DA SromClk_H 2.0 ns 2.0 ns NA 100 mV/ns
SromOE_L O_OD EV6Clk_x NA NA ± 2.0 ns
SromClk_H
20
O_OD EV6Clk_x NA NA ±7.0ns
Tms_H I_DA Tck_H 2.0 ns 2.0 ns NA NA 100 mV/ns
Trst_L
21
I_DA Tck_H NANANA NA 100 mV/ns
Tdi_H I_DA Tck_H 2.0 ns 2.0 ns NA NA 100 mV/ns
Tdo_H O_OD Tck_H NA NA ± 7.0 ns NA NA
Tck _H I_DA IEEE 1149.1 Port Freq. = 5.0
MHz Max.
NA NA NA 45-55% 100 mV/ns
TestStat_H O_OD EV6Clk_x NA NA ± 4.0 ns NA NA
1
The TSU specified for all clock-forwarded signal groups is with respect to the associated clock.
Table 9–13 AC Specifications (Continued)
Signal Name Type Reference Signal TSU
1
TDH
2
TSkew Duty Cycle TSlew