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6–4 Privileged Architecture Library Code
21264/EV68A Hardware Reference Manual
Opcodes Reserved for PALcode
Figure 6–1 HW_LD Instruction Format
Table 6–3 describes the HW_LD instruction fields.
6.4.2 HW_ST Instruction
PALcode uses the HW_ST instruction to access memory outside the realm of normal
Alpha memory management and to do special forms of Dstream store instructions. Data
alignment traps are inhibited for HW_ST instructions. Figure 6–2 shows the HW_ST
instruction format.
Figure 6–2 HW_ST Instruction Format
Table 6–3 HW_LD Instruction Fields Descriptions
Extent Mnemonic Value Description
[31:26] OPCODE 1B
16
The opcode value.
[25:21] RA — Destination register number.
[20:16] RB — Base register for memory address.
[15:13] TYPE 000
2
Physical — The effective address for the HW_LD instruction is physical.
001
2
Physical/Lock — The effective address for the HW_LD instruction is
physical. It is the load lock version of the HW_LD instruction.
010
2
Virtual/VPTE — Flags a virtual PTE fetch (LD_VPTE). Used by trap logic
to distinguish a single TB miss from a double TB miss. Kernel mode access
checks are performed.
100
2
Virtual — The effective address for the HW_LD instruction is virtual.
101
2
Virtual/WrChk — The effective address for the HW_LD instruction is
virtual. Access checks for fault-on-read (FOR), fault-on-write (FOW), read
and write protection.
110
2
Virtual/Alt — The effective address for the HW_LD instruction is virtual.
Access checks use DTB_ALT_MODE IPR.
111
2
Virtual/WrChk/Alt — The effective address for the HW_LD instruction is
virtual. Access checks for FOR, FOW, read and write protection. Access
checks use DTB_ ALT_MODE IPR.
[12] LEN 0
1
Access length is longword.
Access length is quadword.
[11:0] DISP — Holds a 12-bit signed byte displacement.
31 26 25 21 20 16 15 13 1112 0
FM-05654.AI4
TYPE
LEN
DISP
RBRA
OPCODE
31 26 25 21 20 16 15 13 1112 0
FM-05654.AI4
TYPE
LEN
DISP
RBRA
OPCODE