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3–6 Hardware Interface
21264/EV68A Hardware Reference Manual
21264/EV68A Signal Names and Functions
Table 3–3 lists signals by function and provides an abbreviated description.
SysVref I_DC_REF 1 System interface reference voltage.
Tck_H I_DA 1 IEEE 1149.1 test clock.
Tdi_H I_DA 1 IEEE 1149.1 test data-in signal.
Tdo_H O_OD_TP 1 IEEE 1149.1 test data-out signal.
TestStat_H O_OD_TP 1 Test status pin. System reset drives the test status pin low.
The TestStat_H pin is forced high at the start of the Icache
BiST. If the Icache BiST passes, the pin is deasserted at the end
of the BiST operation; otherwise, it remains high.
The 21264/EV68A generates a timeout reset signal if an
instruction is not retired within one billion cycles.
The 21264/EV68A signals the timeout reset event by output-
ting a 256 GCLK cycle wide pulse on TestStat_H.
Tms_H I_DA 1 IEEE 1149.1 test mode select signal.
Trst_L I_DA 1 IEEE 1149.1 test access port (TAP) reset signal.
Table 3–3 21264/EV68A Signal Descriptions by Function
Signal Type Count Description
BcVref Domain
BcAdd_H[23:4] O_PP 20 Bcache index.
BcCheck_H[15:0] B_DA_PP 16 ECC check bits for BcData_H[127:0].
BcData_H[127:0] B_DA_PP 128 Bcache data.
BcDataInClk_H[7:0] I_DA 8 Bcache data input clocks.
BcDataOE_L O_PP 1 Bcache data output enable.
BcDataOutClk_H[3:0]
BcDataOutClk_L[3:0]
O_PP 8 Bcache data output clocks.
BcDataWr_L O_PP 1 Bcache data write enable.
BcLoad_L O_PP 1 Bcache burst enable.
BcTag_H[42:20] B_DA_PP 23 Bcache tag bits.
BcTagDirty_H B_DA_PP 1 Tag dirty state bit.
BcTagInClk_H I_DA 1 Bcache tag input clock.
BcTagOE_L O_PP 1 Bcache tag output enable.
BcTagOutClk_H
BcTagOutClk_L
O_PP 2 Bcache tag output clocks.
BcTagParity_H B_DA_PP 1 Tag parity state bit.
BcTagShared_H B_DA_PP 1 Tag shared state bit.
BcTagValid_H B_DA_PP 1 Tag valid state bit.
BcTagWr_L O_PP 1 Tag RAM write enable.
Table 3–2 21264/EV68A Signal Descriptions (Continued)
Signal Type Count Description