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21264/EV68A Hardware Reference Manual
external cache
See second-level cache.
FEPROM
Flash-erasable programmable read-only memory. FEPROMs can be bank- or bulk-
erased. Contrast with EEPROM.
FET
Field-effect transistor.
FEU
The unit within the 21264/EV68A microprocessor that performs floating-point calcula-
tions.
firmware
Machine instructions stored in nonvolatile memory.
floating point
A number system in which the position of the radix point is indicated by the exponent
part and another part represents the significant digits or fractional part.
flush
See cache flush.
forwarded clock
A single-ended differential signal that is aligned with its associated fields. The for-
warded clock is sourced and aligned by the sender with a period that is two times the bit
time. Forwarded clocks must be 50% duty cycle clocks whose rising and falling edges
are aligned with the changing edge of the data.
FPGA
Field-programmable gate array.
FPLA
Field-programmable logic array.
FQ
Floating-point issue queue.
framing clock
The framing clock defines the start of a transmission either from the system to the
21264/EV68A or from the 21264/EV68A to the system. The framing clock is a power-
of-2 multiple of the 21264/EV68A GCLK frequency, and is usually the system clock.
The framing clock and the input oscillator can have the same frequency. The
add_frame_select IPR sets that ratio of bit times to framing clock. The frame clock
could have a period that is four times the bit time with a add_frame_select of 2X.
Transfers begin on the rising and falling edge of the frame clock. This is useful for sys-
tems that have system clocks with a period too small to perform the synchronous reset