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9: Debugging Your System
9-6 EPSON ARM720T CORE CPU MANUAL
9.3.1 Entry into debug state on breakpoint
The ARM720T processor marks instructions as being breakpointed as they enter the
instruction pipeline, but the core does not enter debug state until the instruction reaches the
Execute stage.
Breakpointed instructions are not executed. Instead, the ARM720T core enters debug state.
When you examine the internal state, you see the state before the breakpointed instruction.
When your examination is complete, remove the breakpoint. Program execution restarts from
the previously-breakpointed instruction.
When a breakpointed conditional instruction reaches the Execute stage of the pipeline, the
breakpoint is always taken if the system is in halt mode. The ARM720T core enters debug
state regardless of whether the instruction condition is met.
A breakpointed instruction does not cause the ARM720T core to enter debug state when:
• A branch or a write to the PC precedes the breakpointed instruction. In this case,
when the branch is executed, the ARM720T processor flushes the instruction
pipeline, so canceling the breakpoint.
• An exception occurs, causing the ARM720T processor to flush the instruction
pipeline, and cancel the breakpoint. In normal circumstances, on exiting from an
exception, the ARM720T core branches back to the instruction that would have
been executed next before the exception occurred. In this case, the pipeline is
refilled and the breakpoint is reflagged.
9.3.2 Entry into debug state on watchpoint
Watchpoints occur on data accesses. In halt mode, the core processing stops. In monitor mode,
an abort exception is executed (see
Abort
on page 2-12). A watchpoint is always taken, but a
core in halt mode might not enter debug state immediately because the current instruction
always completes. If the current instruction is a multiword load or store (an LDM or STM),
many cycles can elapse before the watchpoint is taken.
On a watchpoint, the following sequence occurs:
1 The current instruction completes.
2 All changes to the core state are made.
3 Load data is written into the destination registers.
4 Base write-back is performed.
Note: Watchpoints are similar to Data Aborts. The difference is that when a Data Abort
occurs, although the instruction completes, the ARM720T core prevents all
subsequent changes to the ARM720T processor state. This action enables the abort
handler to cure the cause of the abort, so the instruction can be re-executed.
If a watchpoint occurs when an exception is pending, the core enters debug state in the same
mode as the exception.