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CONTENTS
ARM720T CORE CPU MANUAL EPSON i
Contents
Preface
About this document................................................................................................xi
1 Introduction
1.1 About the ARM720T processor ................................................................. 1-1
1.2 Coprocessors ............................................................................................ 1-5
1.3 About the instruction set ............................................................................ 1-5
1.4 Silicon revisions....................................................................................... 1-18
2 Programmer’s Model
2.1 Processor operating states........................................................................ 2-1
2.2 Memory formats......................................................................................... 2-2
2.3 Instruction length ....................................................................................... 2-3
2.4 Data types ................................................................................................. 2-3
2.5 Operating modes ....................................................................................... 2-4
2.6 Registers ................................................................................................... 2-4
2.7 Program status registers ........................................................................... 2-8
2.8 Exceptions ............................................................................................... 2-10
2.9 Relocation of low virtual addresses by the FCSE PID............................. 2-15
2.10 Reset ....................................................................................................... 2-16
2.11 Implementation-defined behavior of instructions ..................................... 2-17
3 Configuration
3.1 About configuration.................................................................................... 3-1
3.2 Internal coprocessor instructions............................................................... 3-2
3.3 Registers ................................................................................................... 3-3
4 Instruction and Data Cache
4.1 About the instruction and data cache ........................................................ 4-1
4.2 IDC validity ................................................................................................ 4-2
4.3 IDC enable, disable, and reset .................................................................. 4-2
5 Write Buffer
5.1 About the write buffer ................................................................................ 5-1
5.2 Write buffer operation ................................................................................ 5-2
6 The Bus Interface
6.1 About the bus interface.............................................................................. 6-1
6.2 Bus interface signals ................................................................................. 6-3
6.3 Transfer types............................................................................................ 6-5
6.4 Address and control signals ...................................................................... 6-7
6.5 Slave transfer response signals ................................................................ 6-9
6.6 Data buses .............................................................................................. 6-10
6.7 Arbitration ................................................................................................ 6-12
6.8 Bus clocking ............................................................................................ 6-13