Filter
Top Products
9: Debugging Your System
ARM720T CORE CPU MANUAL EPSON 9-13
9.9.2 Restrictions on monitor-mode debugging
There are several restrictions you must be aware of when the ARM core is configured for
monitor-mode debugging:
• Breakpoints and watchpoints cannot be data-dependent in monitor mode. No
support is provided for use of the range functionality. Breakpoints and watchpoints
can only be based on the following:
– instruction or data addresses
– external watchpoint conditioner (DBGEXT[0] or DBGEXT[1])
– User or privileged mode access (CPnTRANS)
– read/write access for watchpoints (HWRITE)
– access size (watchpoints SIZE[1:0]).
• External breakpoints or watchpoints are not supported.
• No support is provided to mix halt mode and monitor mode functionality.
The fact that an abort has been generated by the monitor mode is recorded in the abort status
register in coprocessor 14 (see
Abort status register
on page 9-38).
The monitor mode enable bit does not put the ARM720T processor into debug state. For this
reason, it is necessary to change the contents of the watchpoint registers while external
memory accesses are taking place, rather than changing them when in debug state where the
core is halted.
If there is a possibility of false matches occurring during changes to the watchpoint registers
(caused by old data in some registers and new data in others) you must:
1 Disable the watchpoint unit by setting bit 5 in the Debug Control Register (also
known as the EmbeddedICE-RT disable bit).
2 Poll the Debug Control Register until the EmbeddedICE-RT disable bit is read back
as set.
3 Change the other registers.
4 Re-enable the watchpoint unit by clearing the EmbeddedICE-RT disable bit in the
Debug Control Register.
See
Debug control register
on page 9-39 for more information about controlling core behavior
at breakpoints and watchpoints.