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11: Test Support
11-8 EPSON ARM720T CORE CPU MANUAL
; Now read and check
MOV r8,#8
MOV r2,#0x10
MOV r1,#0
loop1 MCR p15,3,r1,c15,c3,0 ; write C15.C to ‘0’
MCR p15,2,r2,c15,c11,2 ; read RAM to C15.C
MRC p15,3,r5,c15,c3,0 ; read C15.C to R4
ADD r2,r2,#0x04
CMP r5,r0
BNE TEST_FAIL
SUBS r8,r8,#1
BNE loop1
B TEST_PASS
11.5 MMU test registers and operations
The TLB is maintained using MCR and MRC instructions to CP15 registers c2, c3, c5, c6, c8,
and c10, defined by the ARM v4T programmer’s model.
The CP15 register c2 operations control the
Translation Table Base
(TTB). These operations
are:
• write Translation Table Base Registers
• read Translation Table Base Register.
The CP15 register c3 operations control the
Domain Access Control
(DAC) register. These
operations are:
• write DAC registers
• read DAC register.
The CP15 register c5 operations control the
Fault Status Register
(FSR). These operations are:
•write FSR
•read FSR.
The CP15 register c6 operations control the
Fault Address Register
(FAR). These operations
are:
•write FAR
• read FAR.
The CP15 register c8 operations control the TLB and are all write-only. These operations are:
• invalidate TLB
• invalidate single entry using MVA.
The CP15 register c10 operations control TLB lockdown. These operations are:
• read victim, lockdown base and preserve bit
• write victim, lockdown base and preserve bit.