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6: The Bus Interface
6-4 EPSON ARM720T CORE CPU MANUAL
The AHB bus master interface signals are shown in Figure 6-2.
Figure 6-2 AHB bus master interface
AHB master
HBUSREQ
HLOCK
HREADY
HRESETn HWRITE
HCLKEN
HCLK
HTRANS[1:0]
HRDATA[31:0]
HWDATA[31:0]
HPROT[3:0]
HBURST[2:0]
HSIZE[2:0]
HADDR[31:0]
HRESP[1:0]
HGRANTArbiter grant
Data
Reset
Clock
Transfer type
Data
Address
and control
Arbiter
Transfer
response