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CONTENTS
ii EPSON ARM720T CORE CPU MANUAL
6.9 Reset ....................................................................................................... 6-13
7 Memory Management Unit
7.1 About the MMU.......................................................................................... 7-1
7.2 MMU program-accessible registers ........................................................... 7-3
7.3 Address translation .................................................................................... 7-4
7.4 MMU faults and CPU aborts .................................................................... 7-15
7.5 Fault address and fault status registers................................................... 7-16
7.6 Domain access control ............................................................................ 7-17
7.7 Fault checking sequence ......................................................................... 7-19
7.8 External aborts......................................................................................... 7-21
7.9 Interaction of the MMU and cache........................................................... 7-21
8 Coprocessor Interface
8.1 About coprocessors ................................................................................... 8-1
8.2 Coprocessor interface signals ...................................................................8-3
8.3 Pipeline-following signals........................................................................... 8-4
8.4 Coprocessor interface handshaking .......................................................... 8-5
8.5 Connecting coprocessors ..........................................................................8-9
8.6 Not using an external coprocessor .......................................................... 8-10
8.7 STC operations........................................................................................ 8-10
8.8 Undefined instructions ............................................................................. 8-10
8.9 Privileged instructions.............................................................................. 8-10
9 Debugging Your System
9.1 About debugging your system ................................................................... 9-2
9.2 Controlling debugging................................................................................9-3
9.3 Entry into debug state................................................................................9-5
9.4 Debug interface ......................................................................................... 9-9
9.5 ARM720T core clock domains................................................................... 9-9
9.6 The EmbeddedICE-RT macrocell............................................................ 9-10
9.7 Disabling EmbeddedICE-RT.................................................................... 9-11
9.8 EmbeddedICE-RT register map .............................................................. 9-12
9.9 Monitor mode debugging .........................................................................9-12
9.10 The debug communications channel ....................................................... 9-14
9.11 Scan chains and the JTAG interface ....................................................... 9-17
9.12 The TAP controller................................................................................... 9-19
9.13 Public JTAG instructions.......................................................................... 9-20
9.14 Test data registers ................................................................................... 9-22
9.15 Scan timing .............................................................................................. 9-25
9.16 Examining the core and the system in debug state ................................. 9-26
9.17 Exit from debug state...............................................................................9-29
9.18 The program counter during debug ......................................................... 9-30
9.19 Priorities and exceptions.......................................................................... 9-32
9.20 Watchpoint unit registers ......................................................................... 9-33
9.21 Programming breakpoints........................................................................9-36
9.22 Programming watchpoints ....................................................................... 9-38
9.23 Abort status register.................................................................................9-38
9.24 Debug control register ............................................................................. 9-39
9.25 Debug status register............................................................................... 9-41
9.26 Coupling breakpoints and watchpoints .................................................... 9-43
9.27 EmbeddedICE-RT timing......................................................................... 9-44