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5: Write Buffer
5-2 EPSON ARM720T CORE CPU MANUAL
5.2 Write buffer operation
You control the operation of the write buffer with CP15 register 1, the Control Register (see
Control Register
on page 3-4).
When the CPU performs a write operation, the translation entry for that address is inspected
and the state of the B bit determines the subsequent action. If the write buffer is disabled
using the Control Register, buffered writes are treated in the same way as unbuffered writes.
To enable the write buffer:
1 Ensure that the MMU is enabled by setting bit 0 in the Control Register.
2 Enable the write buffer by setting bit 3 in the Control Register.
You can enable the MMU and write buffer simultaneously with a single write to the
Control Register.
To disable the write buffer, clear bit 3 in the Control Register. Any writes already in the write
buffer complete normally. The write buffer attempts a write operation as long as there is data
present.
5.2.1 Bufferable write
If the write buffer is enabled and the processor performs a write to a bufferable area, the data
is placed in the write buffer at the speed of HCLK, and the CPU continues execution. The write
buffer then performs the external write in parallel.
If the write buffer is full, the processor is stalled until there is an empty line in the buffer.
5.2.2 Unbufferable write
If the write buffer is disabled or the CPU performs a write to an unbufferable area,
the processor is stalled until the write buffer empties and the write completes externally. This
might require synchronization and several external clock cycles.
5.2.3 Read-lock-write
The write phase of a read-lock-write sequence (SWP instruction) is treated as an unbuffered
write, even if it is marked as buffered.
5.2.4 Reading from a noncachable area
If the CPU performs a read from a noncachable area, the write buffer is drained and the
processor is stalled.
5.2.5 Draining the write buffer
You can force a drain of the write buffer by performing a read from a noncachable location.
5.2.6 Multi-word writes
All accesses are treated as nonsequential, which means that writes require an address slot and
a data slot for each word. For this reason, buffered STM accesses could be less efficient than
unbuffered STM accesses. You are advised to disable the write buffer (by clearing bit 3 in CP15
register 1) before moving large blocks of data.