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6: The Bus Interface
ARM720T CORE CPU MANUAL EPSON 6-13
6.8 Bus clocking
There are two clock inputs on the ARM720T processor bus interface.
6.8.1 HCLK
The bus is clocked by the system clock, HCLK. This clock times all bus transfers. All signal
timings are related to the rising edge of HCLK.
6.8.2 HCLKEN
HCLK is enabled by the HCLKEN signal. You can use HCLKEN to slow the bus transfer rate
by dividing HCLK for the bus interface.
Note: HCLKEN is not a clock enable for the CPU itself, but only for the bus. Use
HREADY to insert wait states on the bus.
6.9 Reset
The bus reset signal is HRESETn. This signal is the global reset, used to reset the system and
the bus. It can be asserted asynchronously, but is deasserted synchronously after the rising
edge of HCLK. Complete system reset is achieved when DBGnTRST is asserted in the same
way as HRESETn.
During reset, all masters must ensure the following:
• the address and control signals are at valid levels
• HTRANS[1:0] indicates IDLE.
HRESETn is the only active LOW signal in the AMBA AHB specification.