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9: Debugging Your System
ARM720T CORE CPU MANUAL EPSON 9-21
9.13.3 IDCODE (b1110)
The IDCODE instruction connects the device identification code register (or ID register)
between DBGTDI and DBGTDO. The ID register is a 32-bit register that enables the
manufacturer, part number, and version of a component to be read through the TAP. See
ARM720T processor device identification (ID) code register
on page 9-22 for the details of the
ID register format.
When the IDCODE instruction is loaded into the instruction register, all the scan cells are
placed in their normal (system) mode of operation:
• In the CAPTURE-DR state, the device identification code is captured by the ID
register.
• In the SHIFT-DR state, the previously captured device identification code is shifted
out of the ID register through the DBGTDO pin, while data is shifted into the ID
register through the DBGTDI pin.
• In the UPDATE-DR state, the ID register is unaffected.
9.13.4 BYPASS (b1111)
The BYPASS instruction connects a 1-bit shift register (the bypass register) between DBGTDI
and DBGTDO.
When the BYPASS instruction is loaded into the instruction register, all the scan cells assume
their normal (system) mode of operation. The BYPASS instruction has no effect on the system
pins:
• In the CAPTURE-DR state, a logic 0 is captured the bypass register.
• In the SHIFT-DR state, test data is shifted into the bypass register through
DBGTDI and shifted out on DBGTDO after a delay of one HCLK cycle. The first bit
to shift out is a zero.
• The bypass register is not affected in the UPDATE-DR state.
All unused instruction codes default to the BYPASS instruction.
9.13.5 RESTART (b0100)
The RESTART instruction restarts the processor on exit from debug state. The RESTART
instruction connects the bypass register between DBGTDI and DBGTDO. The TAP controller
behaves as if the BYPASS instruction had been loaded.
The processor exits debug state when the RUN-TEST/IDLE state is entered.
For more information, see
Exit from debug state
on page 9-29.