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Write-Back Cache
Write operations are also performed on the cache. Transfer to standard
memory is done if:
− Memory is needed in the cache for another operation
− Modified data in the cache is needed for another application
The third level of cache or L3 cache is sometimes referred to as a victim cache.
This cache is a highly customized cache used to store recently evicted L2 cache
entries. It is a smaller cache usually less than 256 bytes. An L3 cache is
implemented in the IBM PC Server 720 SMP system.
1.3.1.1 SMP Caching
Within SMP designs, there are two ways in which a cache is handled:
•
Shared cache
•
Dedicated cache
Shared Cache:
Sharing a single L2 cache among processors is the least
expensive SMP design. However, the performance gains associated with a
shared cache are not as great as with a dedicated cache. With the shared
secondary cache design, adding a second processor can provide as much as a
30% performance improvement. Additional processors provide very little
incremental gain. If two many processors are added, the system will even run
slower due to memory bus bottlenecks caused by processor contention for
access to system memory.
The IBM PC server 320 supports SMP with a shared cache.
Figure 1 shows SMP with shared secondary cache.
┌───────────────┐ ┌───────────────┐
│ Pentium │ │ Pentium │
└───────┬───────┘ └───────┬───────┘
││
││
││
└────────────────┬────────────────┘
│
│
│
│
│
┌──────────────────┴────────────────────┐
│ 512KB Secondary (level2) Cache │
└──────────────────┬────────────────────┘
│
│
│
┌────────┴─────────┐
│ Main memory │
└────────┬─────────┘
│
Figure 1. SMP Shared Secondary Cache
Chapter 1. IBM PC Server Technologies 5