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Figure 6 on page 11 shows the implementation of ECC-P. When ECC-P is
enabled via the reference diskette, the controller reads/writes two 32-bit words
and 8 bits of check information to standard parity memory. Since 8 check bits
are available on a 64-bit word, the system is able to correct single-bit errors and
detect double-bit errors just like ECC memory.
┌───────────────────┐ ┌───────────────────┐
││││
││││
├─────────┬┬────────┤ ├─────────┬┬────────┤
│ 32 data ││4 parity│ │ 32 data ││4 parity│
└────┬────┘└───┬────┘ └─────┬───┘└────┬───┘
││ ││
│ └───────────────┬──────────┼─────────┘
│││
└─────────────────────┬───┼──────────┘
64 bits for data │ │
│ │8 bits for ECC
┌──┴───┴─────┐
│ Memory │
│ Controller │
└────────────┘
Figure 6. ECC-P Memory Implementation
While ECC-P uses standard non-expensive memory, it needs a specific memory
controller that is able to read/write the two memory blocks and check and
generate the check bits. Also, the additional logic necessary to implement the
ECC circuitry make it slightly slower than true ECC memory. Since the price
difference between a standard memory SIMM and an ECC SIMM has narrowed,
IBM no longer implements ECC-P.
1.4.4 ECC on SIMMs (EOS) Memory
A server that supports one hundred or more users can justify the additional cost
necessary to implement ECC on the system. It is harder to justify this cost for
smaller configurations. It would be desirable for a customer to be able to
upgrade his system at a reasonable cost to take advantage of ECC memory as
his business grows.
The problem is that the ECC and ECC-P techniques previously described use
special memory controllers imbedded on the planar board which contain the
ECC circuits. It is impossible to upgrade a system employing parity memory
(with a parity memory controller) to ECC even if we upgrade the parity memory
SIMMs to ECC memory SIMMs.
To answer this problem, IBM has introduced a new type of memory SIMM which
has the ECC logic integrated on the SIMM. These are called ECC on SIMMs or
EOS memory SIMMs. With these SIMMs, the memory error is detected and
corrected directly on the SIMM before the data gets to the memory controller.
This solution allows a standard memory controller to be used on the planar
board and allows the customer to upgrade a server to support error checking
memory.
Chapter 1. IBM PC Server Technologies 11