Intel 31154 Computer Hardware User Manual


 
10 Intel
®
31154 133 MHz PCI Bridge Design Guide Design Guide
Introduction
The 31154 has additional hardware support for CompactPCI* Hot Swap and Redundant System
Slot via queue flush, arbiter lock, and clock output tristating.
The 31154 supports any combination of 32-bit and 64-bit data transfers on its primary and
secondary bus interfaces. The 31154 is 33/66 MHz capable in conventional PCI mode, and can run
at 66 MHz, 100 MHz, or 133 MHz when operating in PCI-X mode, depending upon its
surrounding environment.
2.2 Features List
Table 3. Features List
PCI bus interfaces (2):
PCI Local Bus Specification,
Revision 2.3 compliant
PCI-to-PCI Bridge Architecture
Specification, Revision 1.2 compliant
PCI Bus Power Management
Interface Specification, Revision 1.1
compliant
PCI-X Addendum to the PCI Local
Bus Specification, Revision 1.0b
compliant
External SROM support
Vital Products Data (VPD) support
64-bit initiator/target capable
64-bit addressing
Hardware support for dual-host cPCI
configurations
Compact PCI Hot Swap Specification,
Revision 2.1 R2.0 support
Secondary clock generation with 10 clock
outputs
Secondary bus arbitration:
Internal arbiter supports nine agents in
addition to the 31154.
Internal arbiter can be disabled.
Optimized for PCI-X mode
Bus parking on bridge or last master
Improved buffer architecture:
8 KBytes data buffers in each
direction
Improved level of concurrency:
Up to nine outstanding transactions on
each bus simultaneously
Scalability and flexibility:
Conventional PCI 32/64-bit
33/66 MHz, 3.3 V
5 V tolerant inputs
PCI-X 32/64-bit 66/100/133 MHz,
3.3 V
JTAG interface
GPIO interface:
Allows simple software-controlled
signaling protocols