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Intel
®
31154 133 MHz PCI Bridge Design Guide 3
Contents
Contents
1 About This Document......................................................................................................................7
1.1 Terminology and Definitions .................................................................................................7
2 Introduction......................................................................................................................................9
2.1 Product Overview .................................................................................................................9
2.2 Features List.......................................................................................................................10
2.3 Related External Specifications..........................................................................................11
2.4 References .........................................................................................................................11
3 Package Information......................................................................................................................13
3.1 Total Signal Count ..............................................................................................................17
4 Terminations..................................................................................................................................19
5 PCI/PCI-X Interface.......................................................................................................................29
5.1 PCI/PCI-X Voltage Levels...................................................................................................29
5.2 Interrupt Routing.................................................................................................................29
5.3 IDSEL Lines........................................................................................................................30
5.3.1 Primary IDSEL Line ...............................................................................................30
5.3.2 Secondary IDSEL Lines.........................................................................................30
5.3.3 Secondary IDSEL Masking....................................................................................31
5.3.4 Secondary Clock Control.......................................................................................31
5.4 CompactPCI* Hot Swap Mode Select ................................................................................31
5.5 Opaque Memory Region Enable ........................................................................................31
5.6 PCI-X Initialization Clocking Modes....................................................................................32
5.6.1 Primary PCI Clocking Mode...................................................................................32
5.6.2 Secondary PCI Clocking Mode..............................................................................32
5.6.3 Primary-to-Secondary Frequency Limits................................................................34
6 Routing Guidelines ........................................................................................................................35
6.1 Crosstalk.............................................................................................................................36
6.2 EMI Considerations ............................................................................................................37
6.3 Power Distribution and Decoupling.....................................................................................38
6.3.1 Decoupling Recommendations..............................................................................38
6.4 Trace Impedance................................................................................................................39
7 PCI-X Layout Guidelines ...............................................................................................................41
7.1 PCI Clock Layout Guidelines..............................................................................................42
7.2 PCI-X Topology Layout Guidelines.....................................................................................44
7.2.1 Single Slot at 133 MHz ..........................................................................................45
7.2.1.1 Intel
®
31154 133 MHz PCI Bridge Embedded Application at 133 MHz.46
7.2.2 Dual-Slot at 100 MHz.............................................................................................47
7.2.2.1 Embedded Intel
®
31154 133 MHz PCI Bridge Application at 100 MHz.48
7.2.3 Quad-Slots at 66 MHz ...........................................................................................49
7.2.3.1 Embedded Intel
®
31154 133 MHz PCI Bridge Application at 66 MHz...51
7.2.4 PCI-X at 33 MHz....................................................................................................52
7.2.4.1 Embedded PCI-X Specification PICMG 1.2 Overview...........................52