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Intel
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31154 133 MHz PCI Bridge Design Guide Design Guide 49
PCI-X Layout Guidelines
7.2.3 Quad-Slots at 66 MHz
Figure 13 shows one of the bridge secondary AD lines branching to four segments with each
segment connecting to a slot connector to a buffer on an add-in card. The first segment representing
an upper address line branches to a series resistor to become the IDSEL line for slot 1. Table 18
shows the corresponding wiring lengths to use as a reference.
Figure 13. Quad-Slots 66 MHz Topology
Table 18. Wiring Lengths for 66 MHz Quad-Slot (Sheet 1 of 2)
Segment
Lower AD Bus Upper AD Bus
Units
Minimum
Length
Maximum
Length
Minimum
Length
Maximum
Length
W1 5 7 2.5 7 inches
W13 0.75 1.5 1.75 2.75 inches
W140.1 0.1 – –inches
B3060-01
W1
W14 W15 W16
W13
I/O Buffer
PCI Connector
W23W22
PCI Agent 2
PCI Agent 3
PCI Agent 4
PCI Agent 1
PCI Connector
W33W32
PCI Connector
W43W42
PCI Connector
Slot 1
Slot 2
Slot 3
Slot 4