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110 Intel
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41210 Serial to Parallel PCI Bridge Developer’s Manual
Register Description
12.2.58 Offset 11C–12Bh: HDR_LOG—PCI Express*
Transaction Header Log
This register is the transaction header log for PCI Express* errors.
Table 92. Offset 11C–12Bh: HDR_LOG—PCI Express* Transaction Header Log
Bits Type Reset Description
127:0 ROS 0
Header of the PCI Express* Packet in Error: As soon as an error is logged in this register,
it remains locked for further error-logging until the software clears the status bit that caused
the header log (in other words, until the error pointer is re-armed for logging again).