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54 Intel
®
41210 Serial to Parallel PCI Bridge Developer’s Manual
Interrupt Support
7.2 Interrupt Routing for Devices behind a Bridge
Given the legacy interrupt sharing scheme shown in Table 23, to get the best legacy interrupt
performance (by reducing interrupt sharing), adapter boards must select the appropriate INTA#–
INTD# input pin to use on each PCI bus segment. The chosen interrupt input also imposes a PCI
device number requirement for the interrupt source as shown in Table 24.
§ §
Table 24. Interrupt Binding for Devices behind a Bridge
Device Number on
Secondary Bus
Interrupt Pin on Device
Interrupt Pin on the Intel
®
41210
Serial to Parallel PCI Bridge
0
1
, 4, 8
2
, 12, 16, 20, 24, 28
INTA# INTA#
INTB# INTB#
INTC# INTC#
INTD# INTD#
1, 5, 9
2
, 13, 17, 21, 25, 29
INTA# INTB#
INTB# INTC#
INTC# INTD#
INTD# INTA#
2, 6, 10
2
, 14, 18, 22, 26, 30
INTA# INTC#
INTB# INTD#
INTC# INTA#
INTD# INTB#
3, 7, 11
2
, 15, 19, 23, 27, 31
INTA# INTD#
INTB# INTA#
INTC# INTB#
INTD# INTC#
NOTES:
1. Device number 0 is reserved for the bridge and must not be assigned to secondary devices.
2. AD[27:24], which correspond to devices[11:8], must not be used for IDSEL# connections, because these
signals are used when accessing the extended configuration space in the bridge from the secondary bus.