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118 Intel
®
41210 Serial to Parallel PCI Bridge Developer’s Manual
Register Description
12.2.65 Offset 170h: SSR—Strap Status Register
This register indicates the status of various reset straps in the 41210.
Table 99. Offset 170h: SSR—Strap Status Register
Bits Type Reset Description
15 RO Strap
Configuration Retry Strap: This bit captures the CFGRETRY strap value at the rising
edge of
PERST#.
14:8 RO 00h
Reserved: Read only
7:1 RO Strap
SMBus Address (SA): These seven bits represent the address to which the SMBus slave
port responds when an access is attempted. This register has the following value:
Only the value from function 0 is valid.
0ROStrap
P133EN Status: This bit reflects the status of the X_133EN pin sampled at the rising edge
of
PERST#.
Bit Value
71
61
5SMBUS[5]
40
3SMBUS[3]
2SMBUS[2]
1SMBUS[1]