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41210 Serial to Parallel PCI Bridge Developer’s Manual 7
Contents
Tables
1 ODT Signals ...............................................................................................................................14
2 PCI Express* Interface Pins .......................................................................................................15
3 PCI Interface Pins.......................................................................................................................16
4 PCI Interface Pins: 64-Bit Extensions.........................................................................................18
5 PCI Clock and Reset Pins ..........................................................................................................18
6 Interrupt Interface Pins ...............................................................................................................19
7 Reset Strap Pins.........................................................................................................................20
8 SMBus Interface Pins .................................................................................................................21
9 Miscellaneous Pins.....................................................................................................................22
10 Miscellaneous Pins.....................................................................................................................23
11 PCI Mode Pin/Strap Encoding....................................................................................................25
12 PCI-X Initialization Pattern..........................................................................................................25
13 PCI Transactions Supported.......................................................................................................26
14 PCI-X Transactions Supported...................................................................................................27
15 LOCK Transaction Handling in the Intel
®
41210 Serial to Parallel PCI Bridge...........................29
16 Intel
®
41210 Serial to Parallel PCI Bridge Implementation of Requester Attribute Fields ..........34
17 Intel
®
41210 Serial to Parallel PCI Bridge Implementation of Completer Attribute Fields ..........35
18 Split Completion Abort Registers................................................................................................35
19 Addressable Spaces within the Intel
®
41210 Serial to Parallel PCI Bridge ................................41
20 Secondary PCI Device Addressing.............................................................................................42
21 Upstream Transaction Ordering .................................................................................................51
22 Downstream Transaction Ordering.............................................................................................52
23 INTx Routing Table.....................................................................................................................53
24 Interrupt Binding for Devices behind a Bridge ............................................................................54
25 SMBus Address Assignments ....................................................................................................55
26 SMBus Command Encoding.......................................................................................................56
27 SMBus Status Byte Encoding.....................................................................................................57
28 Clock Domains............................................................................................................................65
29 Completion-Status Translation for Immediate Terminations.......................................................70
30 Completion-Status Translation for PCI-X Split-Completion Terminations ..................................71
31 Completion-Status Translation for PCI Express* Split-Completion Terminations.......................72
32 Bit Attribute Definitions ...............................................................................................................73
33 Legacy Configuration Space.......................................................................................................76
34 PCI Express* Extended Configuration Space ............................................................................77
35 Offset 00h: ID—Identifiers ..........................................................................................................78
36 Offset 04h: PCICMD—Command Register ................................................................................78
37 Offset 06h: PSTS—Primary Device Status.................................................................................79
38 Offset 08h: REVID—Revision ID ................................................................................................80
39 Offset 09h: CC—Class Code......................................................................................................81
40 Offset 0Ch: CLS—Cache Line Size............................................................................................81
41 Offset 0Dh: PMLT—Primary Master Latency Timer ...................................................................81
42 Offset 0Eh: HEADTYP—Header Type .......................................................................................81
43 Offset 18h: BNUM—Bus Numbers .............................................................................................82
44 Offset 1Bh: SMLT—Secondary Master Latency Timer...............................................................82
45 Offset 1Ch: IOBL—I/O Base and Limit .......................................................................................83
46 Offset 1Eh: SSTS—Secondary Status .......................................................................................84
47 Offset 20h: MBL—Memory Base and Limit ................................................................................85
48 Offset 24h: PMBL—Prefetchable Memory Base and Limit.........................................................86
49 Offset 28h: PMBU32—Prefetchable Memory Base Upper 32 Bits.............................................86