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41210 Serial to Parallel PCI Bridge Developer’s Manual
Addressing
When this bit is cleared, the 41210 forwards transactions addressing the VGA frame buffer
memory and VGA I/O registers from PCI Express* to PCI when the defined memory and I/O
address ranges enable forwarding. When cleared, accesses to the VGA frame buffer memory are
forwarded from PCI to PCI Express* when the defined memory address ranges enable forwarding.
However, the master enable bit must still be set. The VGA I/O addresses are never forwarded to
PCI Express* when the upstream I/O enable bit in BINIT register is cleared. When this bit is set
and also the VGA enable bit is set, the 41210 does not forward the VGA I/O addresses from PCI to
PCI Express*.
The VGA frame buffer consists of the memory address range 000A 0000h–000B FFFFh.
The VGA I/O addresses consist of the I/O addresses 3B0h–3BBh and 3C0h–3DFh. These I/O
addresses are aliased every 1 KB throughout the first 64 KB of I/O space, when the VGA 16-bit
decode bit in the bridge control register (bit[4]) is cleared. This means that address bits[9:0]
(3B0h–3BBh and 3C0h–3DFh) are decoded, bits[15:10] are not decoded and can be any value, and
address bits[31:16] must be all 0s. When the VGA 16-bit decode bit is set, the 41210 does the
entire 16-bit decode on the VGA I/O addresses. When software sets the VGA enable bit in one
bridge, the ISA enable bit must be set in the other bridge.
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