Filter
Top Products
30 Intel
®
41210 Serial to Parallel PCI Bridge Developer’s Manual
PCI-X Interface
3.2.6 Decoding
In the PCI mode, the 41210 supports only the linear increment address mode for bursting memory
transfers (indicated when the lowest two address bits are equal to 0). When either of these address bits
is non-zero, the 41210 disconnects the transaction after the first data transfer. The 41210 decodes all
PCI cycles with medium DEVSEL# timing. In the PCI-X mode, 41210 always decodes as a Type A
target. Also, in PCI-X mode, the 41210 decodes split completions using the primary bus number
field.
Refer to Section 5, “Addressing” on page 41 for a general description of addressing and decoding.
3.2.7 Transaction Termination
3.2.7.1 PCI Mode Transaction Termination
• Normal Termination
As a PCI master, the 41210 uses normal termination when DEVSEL# is returned by the target
within five clock cycles of FRAME# assertion. It terminates a transaction when one of the
following conditions are met:
— All write data for a write transaction are transferred from the 41210 data buffers to the
target (the 41210 does not generate fast back-to-back transactions).
— All read data for a read transaction are transferred from the target to the 41210.
— The master latency timer expires and the bus grant of the 41210 is de-asserted.
• Master Abort
When the transaction initiated by the 41210 does not receive a DEVSEL# response within five
clocks of FRAME# assertion, the 41210 terminates the transaction with a master abort. The
41210 sets the received master abort bit in the secondary status register. Read requests
(configuration, I/O, memory) that receive master abort termination are sent back to PCI
Express*/peer PCI with a master abort status.
Note that when the 41210 performs a Type 1 to special cycle translation, a master abort is the
expected termination for the special cycle on the target bus. In this case, the master abort
received bit is not set, and the Type 1 configuration transaction is disconnected after the first
data phase.
• Target Abort
When the 41210 receives a target abort, and the cycle requires completion on PCI Express*,
the bridge returns the target abort status to PCI Express*. The 41210 sets the received target
abort status bit in the secondary status register for all target aborts it receives on the PCI bus.
Target abort can occur during any data phase of a PCI-X transaction. A read completion packet
to PCI Express*/peer PCI, incurring a target abort in the middle of the packet, returns valid
data to the point of target abort and a target abort completion status for the reminder.
• Disconnect and Retry
When the 41210 receives a disconnect response from a target, it re-initiates the transfer with
the remaining length. When the 41210 receives a retry, it waits at least two PCI clocks before it
retries the transaction. When the retried transaction is a write, the 41210 retries the write until
it completes normally or with a target or master abort. When the retried transaction is a
delayed read or delayed write transaction, the 41210 allows memory reads and writes to pass
the transaction. Refer to Section 6, “Transaction Ordering” on page 51 for details on the kinds