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41210 Serial to Parallel PCI Bridge Developer’s Manual 43
Addressing
The extended address bits used to access the configuration region above 256 B are all 0s when the
access mechanism compatible with the PCI-to-PCI Bridge Specification, Revision 1.1 is used, or
when accessing devices on PCI. Note that 41210, when it translates Type 1 configuration
transactions from PCI Express*-to-PCI and finds the extended address bits to be non-zero,
terminates the transaction with an unsupported request response on PCI Express*. All
configuration accesses on PCI Express* are aligned DWORD only.
• Type 0 accesses to the 41210:
The bridge configuration spaces are accessed from PCI Express* by a Type 0 configuration
transaction. Type 0 transactions from PCI Express* (not peer PCI or SMBus) to the bridge
segments return a configuration retry response on PCI Express* when the “Configuration
Cycle Retry” bit is set in the BINIT register (“Offset FCh: BINIT—Bridge Initialization
Register” on page 104).
The 41210 captures the bus and device numbers from Type 0 configuration writes, to its
internal functions, from PCI Express*. The 41210 does not capture the bus/device number
from Type 0 configuration writes to its internal functions, from either the PCI segment or
SMBus. The captured bus/device number from Type 0 PCI Express* configuration writes are
used by the 41210 in forming the Requester ID/Completer ID on PCI Express* and PCI-X
requests/completions. Also, the 41210 does not decode the device number field for Type 0
configuration transactions from PCI Express*.
• Type 1 accesses to the 41210:
Type 1 accesses from PCI Express* are intended for the PCI bus only and not for the internal
configuration spaces. Type 1 configuration transactions to PCI that do not complete within
40 µs from the time they are received on PCI Express* receive a configuration retry response
on PCI Express* when the retry response is enabled by means of the “Bridge Configuration
Retry Enable” bit in the PCI Express* Device Control Register (“Offset 4Ch: EXP_DCTL—
PCI Express* Device Control Register” on page 93). The 41210 continues to retry the
transaction on PCI even when a retry response has been signaled on PCI Express*, and when
completed, the transaction is discarded.
• Type 1 to Type 0 translation:
The 41210 performs a Type 1 to Type 0 translation when the Type 1 transaction is generated
on PCI Express* and is intended for a device attached directly to its secondary bus. The bridge
must convert the configuration command to a Type 0 format so that the secondary bus device
can respond to it. The resulting Type 0 address is driven on the PCI bus, as shown in Figure 2.
Device numbers are decoded to assert a single bit (IDSEL) in address bits[31:16]. A device
number of 0 converts to PCI AD[16] being a 1; a device number of 2 converts to PCI AD[17]
being a 1; and so on. When the device number is greater than 16, all bits (bits[31:16]) are 0.
See Table 20, “Secondary PCI Device Addressing” on page 42.
Note: When the device-hiding bit in the BINIT register is set, the 41210 master-aborts all Type 0
transactions to the PCI bus targeting device numbers 0 to 9. Device numbers 10 to 15 are never
hidden; in other words, they are never master-aborted.