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Intel
®
440GX AGPset Design Guide
A-3
Intel
®
440GX AGPset Platform Reference Design
Ultra I/O Component 20
This page shows the Ultra I/O component. The RTC may optionally be used. An Infra Red Header
Port is also optional.
AGP Connector 21
This page shows the AGP connector. In this design, AGP INTA and INTB are connected to the PCI
INTA and INTB through a buffer/driver. The interrupt signals are open-collector, and pulled up to
V
CC3.3.
PCI Connectors 22-23
These pages show the PCI connectors. In this design, four PCI connectors are used. AD 26, 27, 29
and 31 are the preferred lines for the PCI slot IDSELs.
ISA Connectors 24
This page shows the ISA connectors.
PCI IDE Connectors 25
This page shows the IDE Connectors. No special logic is required to support Ultra DMA/33 hard
drives.
USB Headers 26
This page shows the USB Headers. Note, the voltage divider on the open circuit signals provides
logic level transitions for the PIIX4E. Note the placement requirements for the capacitors and
series resistors at the bottom left.
Flash BIOS Component 27
This page shows the 28F002BC-T Flash BIOS component which provides 128K bytes of BIOS
memory. A jumper is used to provide the option for allowing the BIOS to be programmed in the
system for BIOS upgrades and/or for programming plug and play information into the Flash
device.
Note that a 2 Meg Flash device may be required for certain applications (motherboard devices such
as graphics, SCSI or LAN).
Parallel Port/ Serial and Floppy/ Keyboard & Mouse 28-30
Nothing new here.
VRM 31
The top of this page shows the voltage regulator modules (VRM 8.2) connectors. The VRM 8.2
module provides 5V to VCCcore voltage conversion for the processor. The bottom of this page
shows two voltage regulators, one for generating the 1.5V GTL+ terminating voltage (V
TT
), the
other is a 2.5V regulator. The V
TT
generation circuit must be able to provide about 5.0 amps of
current under worst case conditions. Note: that two LT1587-1.5s (@ 3A) are recommended.