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Intel
®
440GX AGPset Design Guide
vii
Figures
1-1 Intel
®
Pentium
®
II Processor / Intel
®
440GX AGPset
System Block Diagram..................................................................................1-4
2-1 Major Signal Sections (82443GX Top View).................................................2-1
2-2 Example ATX Placement for a UP Pentium
®
II processor/
Intel
®
440GX AGPset Design .......................................................................2-2
2-3 Example NLX Placement for a UP Intel
®
Pentium
®
II processor /
Intel
®
440GX Design.....................................................................................2-3
2-4 Four Layer Board Stack-up...........................................................................2-4
2-5 Six Layer Board Stack-up With 4 Signal Planes and 2 Power Planes..........2-4
2-6 Six Layer Board Stack-up With 3 Signal Planes and 3 Power Planes..........2-5
2-7 Recommended Topology for Single Processor Design ................................2-6
2-8 Solution Space for Single Processor Design (Based on Results
of Parametric Sweeps)..................................................................................2-7
2-9 Recommended Topology for Dual Processor Design...................................2-8
2-10 Topology for Single Processor Designs With Single-End
Termination (SET).........................................................................................2-9
2-11 Solution Space for Single Processor Designs With Single-End
Termination (SET).........................................................................................2-9
2-12 GTL+ Design Process.................................................................................2-12
2-13 Pre-layout simulation process.....................................................................2-14
2-14 AGP Connector Layout Guidelines.............................................................2-19
2-15 On-board AGP Compliant Device Layout Guidelines .................................2-21
2-16 FET Switch Example...................................................................................2-22
2-17 Registered SDRAM DIMM Example ...........................................................2-23
2-18 Matching the Reference Planes and Adding Decoupling Capacitor ..........2-24
2-19 4 DIMMs (Single or Double-Sided) .............................................................2-24
2-20 Motherboard Model—Data (MDxx), 4 DIMMs.............................................2-25
2-21 Motherboard Model—DQMA[0,2:4,6:7], 4 DIMMs ......................................2-26
2-22 Motherboard Model—DQM_A[1,5], 4 DIMMs .............................................2-26
2-23 Motherboard Model—DQM_A[1,5], 4 DIMMs .............................................2-26
2-24 Motherboard Model—DQM_B[1,5], 4 DIMMs .............................................2-27
2-25 Motherboard Model—CS_A#/CS_B#, 4 DIMMs .........................................2-27
2-26 Motherboard Model—SRAS_A#, 4 DIMMs.................................................2-27
2-27 Motherboard Model—Data (MDxx) Lines, 4 DIMMs (No FET) ...................2-30
2-28 PCI Bus Layout Example............................................................................2-31
2-29 82443GX Decoupling..................................................................................2-31
2-30 Clock Trace Spacing Guidelines.................................................................2-32
2-31 AGP Clock Layout.......................................................................................2-34
3-1 Pull-up Resistor Example..............................................................................3-2
3-2 GCKE & DCLKWR Connections...................................................................3-9
3-3 Current Solution With Existing FET Switches .............................................3-15
3-4 Series Resistor Placement for Primary IDE Connectors.............................3-21
3-5 Dual Footprint Flash Layouts......................................................................3-25
3-6 nterfacing Intel’s Flash with PIIX4E in Desktop ..........................................3-26
3-7 Interfacing Intel’s Flash with PIIX4E in Desktop .........................................3-28
3-8 PWRGOOD & PWROK Logic.....................................................................3-29
4-1 LAI Probe Input Circuit..................................................................................4-3