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Intel
®
440GX AGPset Design Guide
3-9
Design Checklist
3.4.2 CKBF - SDRAM 1 to 18 Clock Buffer
•
A 4.7K ohm pull-up to VCC
3.3
on the OE pin is needed to enable the buffer.
•
Note that DCLKRD pin has been changed to a no connect (NC). The DCLKRD functionality
has been combined with DCLKWR. If desire to remove the trace going to DCLKRD pin, the
capacitor value should be adjusted to compensate for the capacitance change.
•
An I
2
C interface is provided which allows the BIOS to disable unused SDRAM clocks to
reduce EMI and power consumption. It is recommended that the BIOS disable unused clocks.
•
No series termination is required for the SDRAM clocks between the CKBF and the DIMMs.
•
DCLKO from the 82443GX to the CKBF should have a 22 ohm series resistor placed at the
82443GX, and a 47 ohm series resistor placed at the CKBF. This has been shown in
simulations to improve the signal integrity of this signal.
•
Check with your clock vendor and the reference schematics for special layout and decoupling
considerations. The reference schematics implement an LC filter on the supply pins to reduce
noise.
3.4.3 GCKE and DCLKWR Connection
•
See the diagram below for implementation of the 16-bit flip-flop for CKE generation for 4
DIMMs.
•
GCKE trace length from the 82443GX to the flip-flop is recommended to be 1” MIN to 4”
MAX. CKE trace lengths from the flip-flop to the DIMMS is recommended to be 3”.
NOTES:
1. The above circuitry only applies to unbuffer DIMMS. GCKE needs to be disabled for register DIMMS.
2. Pin AB22 has been changed to a no connect (NC), The 82443GX does not have an internal connection for
pin AB22. Existing designs connected DCLKWR & AB22 nets on the motherboard. Since the 82443GX does
not have an internal connection for pin AB22, it will cause a slightly reduced load capacitance on the net. To
avoid additional clock skew on existing designs, a discrete capacitor larger than the 20pF capacitor
recommended may be required.
Figure 3-2. GCKE & DCLKWR Connections
74LVCH16374
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
1 EN
2 EN
C1
C2
82443GX
CKBF
GND
1D3, 1D4
1D5, 1D6
1D7, 1D8
2D1, 2D2
2D3, 2D4
2D5, 2D6
2D7, 2D8
CKE7
CKE6
CKE5
CKE4
CKE3
CKE2
CKE1
CKE0
GCKE
DCLKWR
NC (AB22)
20pF
27pF
v007
- Clock signals fed back into 82443GX and
D-FF must ‘T’-off with equal trace length
and as close as possible to the 82443GX and
D-FF.
- The capacitors must be placed close to the
node where the clock signals are ‘T’-ed.
- The capacitor values are shown.