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Intel
®
440GX AGPset Design Guide
3-6
Design Checklist
used by other logic requiring CMOS/TTL logic levels. The VID lines on the Slot 1 connector
are 5V tolerant.
•
Vcc (±5%) should be provided to the Slot 1 signal Vcc pin B109. This power connection is not
used by the Intel
®
Pentium
®
II processor. It is required for the Slot 1 EMT tool and may be
required by future Boxed processors.
•
The JTAG port must be properly terminated even if it is not used. See the Debug
Recommendations for further information that may affect these resistor values.
•
The EMI pins of the Slot 1 connector (pins B1, B41, B61, B81 and B100) should be connected
to system or chassis ground through zero ohm resistors. The determination to install these
resistors is design dependent and can be determined through empirical methods.
•
TRST# must be driven low during reset to all components with TRST# pins. Connecting a
pull-down resistor to TRST# will accomplish the reset of the port.
•
If two Vtt regulators are used, one at each end of the bus, Intel recommends connecting the two
regulator outputs together with a wide trace that runs the along the same basic path as the
GTL+ signals (beware of crosstalk). V
REF
should be generated at each AGPset component
from this combined V
TT
. This is simply a recommendation to minimize the effects of noise.
See AP-523 Intel
®
Pentium
®
Pro Processor Power Distribution Guidelines for more
information.
•
A single V
TT
regulator may be used. For a UP system a simplistic calculation for maximum
worst case current is 5.0A. This takes into consideration that some signals are not used by the
Intel
®
440GX AGPset.
•
Motherboards planning to support the Boxed Intel
®
Pentium
®
II processor must provide a
matched power header for the Boxed Intel
®
Pentium
®
II processor fan/heatsink power cable
connector. The power header must be positioned within close proximity to the Slot 1
connector.
•
The Slot 1 connector signal SLOTOCC# (Pin B101) is a ground on the Slot 1 processor. The
presence of a CPU core can be determined from a combination of non-zero VID signals, (all
ones designates “No Core”) and if the state of SLOTOCC# is low.
•
ITPREQ[1:0]#, ITPRDY[1:0]# can individually be hooked to either CPU. The ITP .inf file
must match the connections.
•
DBRESET (ITP Reset signal) requires a 240 ohm pull-up to VCC3.